1. Field of the Invention
The present invention relates to a contact hole formation method. More particularly, the present invention relates to a method for forming contact holes in an area in which gate electrodes are densely formed and an area in which gate electrodes are sparsely formed.
2. Description of the Background Art
In recent years, a width of a gate electrode and a pitch between the gate electrodes has become increasingly narrow with the achievement of a high degree of integration of a semiconductor device. Specifically, if a process rule is equal to or smaller than 0.18 μm, the minimum space between adjacent gate electrodes is approximately 0.3 μm, which is extremely narrow. As a result, in the case where the above-described narrow space between the adjacent gate electrodes is filled with an interlayer dielectric, there arises a problem of void formation in the interlayer dielectric between the adjacent gate electrodes.
Therefore, heat treatment is performed for the interlayer dielectric in order to eliminate voids formed between the adjacent gate electrodes. The heat treatment is a process performed for reflowing the interlayer dielectric by heating the interlayer dielectric. The above-described process allows the voids formed between the adjacent gate electrodes to be eliminated.
As a material of the interlayer dielectric for which the above-described heat treatment is performed, it is preferable to use a material which is softened at a low temperature. Because the material softens at a low temperature, transistor characteristics are prevented from being impaired by exposure to an elevated temperature during the heat treatment. For that reason, a boron phosphorous silicate glass (BPSG) film, which reflows at approximately 800 degrees centigrade, is used as the interlayer dielectric. Note that the BPSG film is a dielectric film made out of a silicon oxide film doped with boron (B) and phosphorus (P).
Hereinafter, referring to the drawings, a conventional method for forming contact holes in a semiconductor device using the above-described BPSG film as an interlayer dielectric is described. FIGS. 5A to 5D are cross section views of a semiconductor device in the process of opening contact holes. Before contact holes are opened through the semiconductor device, transistors are formed on a silicon substrate, and an interlayer dielectric is further formed thereon. Note that a cross section view shown in FIG. 5 illustrates a portion of the semiconductor device which functions as a switching device used in a memory, etc.
First, MOS field effect transistors are formed on a silicon substrate 1. Specifically, a gate oxide film (not shown) is formed, and gate electrodes 2 (for example, a polysilicon film) are formed on the gate oxide film. A source region (not shown) and a drain region (not shown) are formed after formation of a gate oxide film (not shown), gate electrodes 2 (for example, a polysilicon film), and side walls 3 (for example, a TEOS film).
Next, a BPSG film 4 is deposited on the gate electrode 2 as an interlayer dielectric. Then, heat treatment is performed for the BPSG film 4 in order to reflow the BPSG film 4. Thus, voids formed between the adjacent gate electrodes 2 are eliminated to the outside of the BPSG film 4. A cross section view of the semiconductor device after the above-described process is shown in FIG. 5A. After completion of the heat treatment, a non-doped oxide film 5 such as a TEOS film, for example, is deposited on the BPSG film 4.
Here, the non-doped oxide film 5 is deposited on the BPSG film 4 for the following reason. The BPSG film 4 is highly hygroscopic. Specifically, when the BPSG film 4 is exposed to the air, boron or phosphorus contained in the BPSG film 4 reacts with water in the air. As a result, compounds of boron, phosphorus, and oxygen, such as BPO4, B2O3, and PO4, for example, are formed and precipitated on the BPSG film 4. The above-described compounds are foreign substances on the BPSG film 4, and substantially reduce yield in the subsequent semiconductor device manufacturing process. Thus, the non-doped oxide film 5, which functions as a protective coat, is deposited on the BPSG film 4 so as to prevent the BPSG film 4 from being exposed to the air.
After deposition of the non-doped oxide film 5 is completed, a surface of the non-doped oxide film 5 is planarized by means of chemical-mechanical polishing (CMP) as shown in FIG. 5B. The above-described planarization is performed so that a photoresist can be accurately formed on the non-doped oxide film in the following process.
Next, a photoresist 6 having an opening 7 is formed on the planarized non-doped oxide film 5 by photolithography. FIG. 5C illustrates the cross section view of the semiconductor device after the above-described process.
Next, as shown in FIG. 5D, dry etching is performed for the non-doped oxide film 5 and the BPSG film 4 using the photoresist 6 as a protective mask for opening a contact hole 8. After the above-described dry etching, the contact hole 8 is filled with metal (for example, tungsten), thereby completing formation of a contact connecting the transistor in the silicon substrate 1 and an interconnection (not shown) formed in an upper layer.
Note that the gate electrodes 2 of the respective transistors are not formed at regular intervals on the silicon substrate 1. As a result, on the silicon substrate 1, gate electrodes 2 are densely formed in some areas and sparsely formed in other areas. The above-described two types of areas, that is, an area in which the gate electrodes 2 are densely formed and an area in which the gate electrodes 2 are sparsely formed, will cause the following problem, which will be described in a concrete manner with reference to the drawings. FIG. 6 is a cross section view of a semiconductor device having an area in which the gate electrodes 2 are densely formed and an area in which the gate electrodes 2 are sparsely formed.
First, as described in FIG. 5A, the BPSG film 4 is formed on the silicon substrate 1 and reflowed by the heat treatment, whereby the voids in the BPSG film 4 are eliminated and the surface of the BPSG film 4 is planarized.
However, if the gate electrodes 2 are densely formed in some areas and sparsely formed in other areas, the surface of the BPSG film 4 becomes uneven, as shown in FIG 6, because density of the gate electrodes 2 varies from area to area even after the above-described heat treatment is performed. Specifically, in the area in which the gate electrodes 2 are densely formed, a film thickness De of the BPSG film 4 becomes thick. On the other hand, in the area in which the gate electrodes 2 are sparsely formed, a film thickness Df of the BPSG film 4 becomes thin. As described above, the heat treatment allows the surface of the BPSG film 4 to be planarized in terms of a local area, such as an area in which the gate electrodes 2 are densely formed or an area in which the gate electrodes 2 are sparsely formed. In terms of the entire area of the semiconductor device, however, the surface of the BPSG film 4 is not planarized. If the non-doped oxide film 5 is deposited on the above-described BPSG film 4 whose surface is not evenly planarized, and the surface of the non-doped oxide film 5 is planarized by means of CMP, a layer composed of the BPSG film 4 and the non-doped oxide film 5 is uniform in thickness, but a thickness ratio of the BPSG film 4 to the non-doped oxide film 5 varies from area to area.
The above-described variations in the thickness ratio cause the following problem at the time of opening of the contact holes. Specifically, the contact holes are opened by removing the BPSG film 4 and the non-doped oxide film 5 by means of dry etching using CxFy gas (for example, C4F8, C5F8, C4F6). Here, an etching rate of the BPSG film 4 is higher than that of the non-doped oxide film 5. As a result, if a thickness ratio of the BPSG film 4 to the non-doped oxide film 5 varies from area to area on the semiconductor device, an etching rate of the interlayer dielectric (that is, a layer composed of the BPSG film 4 and the non-doped oxide film 5) varies from area to area on the semiconductor device. Due to the above-described variations in the etching rate, the opened contact holes vary in depth from area to area on the semiconductor device.
With reference to FIG. 6, a comparison between a depth of a contact hole 8e opened in an area in which the gate electrodes 2 are densely formed and a depth of a contact hole 8f opened in an area in which the gate electrodes 2 are sparsely formed will be described below in a concrete manner. Note that film thicknesses of the BPSG film 4 and the non-doped oxide film 5 are assumed to be De and de, respectively, in an area in which the gate electrodes 2 are densely formed. On the other hand, film thicknesses of the BPSG film 4 and the non-doped oxide film 5 are assumed to be Df and df, respectively, in an area in which the gate electrodes 2 are sparsely formed. Also, note that there are relationships De>Df and de>df among the above-described four film thicknesses.
As shown in FIG. 6, in the area in which the gate electrodes 2 are densely formed, a film of the non-doped oxide film 5 (whose etching rate is relatively higher than that of the BPSG film 4) is thicker, and a film of the BPSG film 4 (whose etching rate is relatively lower than that of the non-doped oxide film 5) is thinner, compared to the area in which the gate electrodes 2 are sparsely formed. As a result, in the area in which the gate electrodes 2 are densely formed, an etching rate of the interlayer dielectric is higher, compared to the area in which the gate electrodes 2 are sparsely formed. Due to the above-described higher etching rate, the bottom of the contact hole 8e reaches the silicon substrate 1 before the bottom of the contact hole 8f reaches the silicon substrate 1, in the case where the contact hole 8e and the contact hole 8f are concurrently formed. As a result, the silicon substrate 1 is also etched in the area in which the gate electrodes 2 are densely formed. If the silicon substrate 1 is also etched as described above, a leakage current occurs, which results in a malfunction of the semiconductor device. On the other hand, in the area in which the gate electrodes 2 are sparsely formed, there is a likelihood that the bottom of the contact hole will not reach the silicon substrate 1, which results in high incidence of breaks within the semiconductor device.
Moreover, the variations in depth of the contact hole, which tapers gently down from an opening to the bottom, results in variations in the area of the bottom of the contact hole, thereby increasing variations in contact resistance.
Note that, in the above descriptions, the silicon substrate 1 having an area in which the gate electrodes 2 are densely formed and an area in which the gate electrodes 2 are sparsely formed has been described. However, the same problem will arise in the case where interconnections are formed on the silicon substrate 1. Specifically, in an area in which a distance between interconnections is narrow, deep contact holes are formed, as in the case of the area in which the gate electrodes 2 are densely formed. On the other hand, in an area in which a distance between interconnections is wide, shallow contact holes are formed, as in the case of the area in which the gate electrodes 2 are sparsely formed. Furthermore, a width of the interconnection as well as the distance between the interconnections also affects the depth of the contact hole. Specifically, in an area in which wide interconnections are formed, deep contact holes are formed, as in the case of the area in which the gate electrodes 2 are densely formed. On the other hand, in an area in which narrow interconnections are formed, shallow contact holes are formed, as in the case of the area in which the gate electrodes 2 are sparsely formed.